Senior RTL Analysis Methodology Engineer
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Position Overview & Specifications
- Serve as in-house expert for static verification EDA tools
- Act as liaison between ASIC designers and EDA vendors.
- Analyze issues, create solutions or workarounds, and provide testcases.
- Evaluate new EDA tools and features and advance verification methodologies.
- Contribute to new design flow development.
- Write technical documents and train internal users.
- Set up and maintain flow regressions and QA.
- Utilize data collection, analysis and reporting tools to provide methodology insights.
- BS in Electrical or Computer Engineering (or equivalent experience), MS preferred
- 3+ years minimum experience with tools and methodologies for ASIC design and verification.
- Direct experience with EDA tools for RTL static checking and verification such as Lint and CDC.
- Strong familiarity with System Verilog and Tcl. Python or Perl knowledge.
- Debugging and problem-solving. Experience working with EDA vendors to resolve problems.
- Very good communication skills
- Synthesis and Equivalence Checking experience is helpful.
Candidate Selection & Onboarding Process
Application & Resume Screening
Submit your tailored CV/Resume directly to the talent acquisition portal.
Technical & Competency Interviews
Virtual interviews with the hiring manager and multidisciplinary team.
Formal Offer & Benefits Negotiation
Written agreement outlining compensation, equity, retirement vesting, and relocation allowances.
Onboarding & Corporate Integration
Equipment provisioning, team orientation, and commencement of duties.
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